The present invention concerns an auxiliary gate lightly doped drain (AGLDD) process for use in producing high reliability submicron metal oxide silicon field effect transistors (MOSFETs).
The use of gate overlapped lightly doped drain (GOLDD) processes to increase reliability of high speed submicron MOSFETs has been investigated. For example, in one process, referred to as total overlap with polysilicon spacer (TOPS), three deposits of polysilicon are use to form a gate region of a transistor which overlaps the source and drain region of the transistor. See J. E. Moon, et al., A New LDD Structure: Total Overlap with Polysilicon Spacer (TOPS), IEEE Electronic Device Letters, May 1990, pp. 221-223. See also T. Y Huang: A novel SubMicron LDD Transistor with inverse-T Gate Structure, IEDM, 1986, pp. 742-745, and R. Izawa, et. al., The Impact of Gate-Drain overlapped LDD(GOLD)/For Deep SubMicron VLSIs, IEDM 1987, pp. 38-41.
However, in such GOLDD structures gate-drain overlap capacitance and gate-source overlap capacitance can result in slow circuit operation speed. In order to reduce gate-drain overlap capacitance and gate-source overlap capacitance, AGLDD processes have been suggested. See for example, Matsatka Minami, Yasuo Sawahata, Hiroshi Matsuki and Takahiro Naganoi, A High Speed and High Reliability MOSFET utilizing an Auxiliary Gate, 1990 Symposium on VLSI Technology, pp. 41-42; and I. C. Chen, J. P. Lin, and C. W. Teng, A Highly Reliable 0.3 .mu.m N-channel MOSFET Using Poly Spacers, 1990 Symposium on VLSI Technology, pp. 39-40.
In the above-cited AGLDD processes, an auxiliary resistor is inserted between the auxiliary and main gates. The value of the auxiliary resistance is selected so that the RC time constant of the auxiliary resistance and the gate-source/drain overlap capacitance is longer than the circuit delay time. This prevents transient circuit action from being affected by the gate-source/drain overlap capacitance. In DC circuit action, however, the auxiliary gate works to increase the high hot-carrier reliability of the circuit.
One drawback of the above-cited prior art AGLDD process described by Matsatka Minami, Yasuo Sawahata, Hiroshi Matsuki and Takahiro Naganoi, High Speed and High Reliability MOSFET utilizing an Auxiliary Gate, 1990 Symposium on VLSI Technology, pp. 41-42, is that the value of the auxiliary resistance is dependent upon a layer of oxide on the sides of the main gate. This oxide layer thickness, however, is difficult to control in a manufacturing environment.